Methods for processing silicon on insulator wafers

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate

Reexamination Certificate

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C438S406000, C438S458000, C438S697000

Reexamination Certificate

active

08080464

ABSTRACT:
Methods are provided for etching and/or depositing an epitaxial layer on a silicon-on-insulator structure comprising a handle wafer, a silicon layer, and a dielectric layer between the handle wafer and the silicon layer. The silicon layer has a cleaved surface defining an outer surface of the structure. The cleaved surface of wafer is then etched while controlling a temperature of the reactor such that the etching reaction is kinetically limited. An epitaxial layer is then deposited on the wafer while controlling the temperature of the reactor such that a rate of deposition on the cleaved surface is kinetically limited.

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PCT International Search Report and Written Opinion of the International Searching Authority mailed on Mar. 9, 2011 regarding PCT/US2010/062094 filed on Dec. 23, 2010.

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