Efficient exhaustive path-based static timing analysis using...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing

Reexamination Certificate

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C716S113000, C716S136000, C703S016000

Reexamination Certificate

active

08079004

ABSTRACT:
One embodiment of the present invention provides a system that performs an efficient path-based static timing analysis (STA) in a circuit design. During operation, the system identifies a set of paths within the circuit design, wherein each path includes one or more segments. For a path in the set of paths, the system determines if at least one segment in the path is shared with a different path which was previously computed by performing a path-based STA, wherein the at least one segment in the different path is associated with previously computed path-based timing information. If so, the system then performs an estimation of a path-based delay for the path based at least on the path-based timing information associated with the shared segment in the different path. Otherwise, the system computes a path-based delay for the path by performing a path-based STA on the path.

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Agarwal, A. et al., “Path-Based Statistical Timing Analysis Considering Inter-and Intra-die Corelations”, In:Proc. TAU, pp. 16-21, 2002.

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