Self-aligned memory cells and method for forming

Details Self-aligned memory cells and method for forming Self-aligned memory cells and method for forming

2008-03-14

2010-11-23

Pert, Evan (Department: 2826)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C438S479000, C438S482000, C438S488000, C438S691000, C365S148000, C257S003000, C257S005000, C257S499000, C257SE31029

Reexamination Certificate

active

07838341

ABSTRACT:
The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

REFERENCES:
patent: 2008/0237566 (2008-10-01), An et al.

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