Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive...
Reexamination Certificate
2008-01-22
2010-11-02
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
C257SE21346, C257SE21552, C257SE21642
Reexamination Certificate
active
07824999
ABSTRACT:
A CMOS device with polysilicon protection tiles is shown in FIG.2. LOCOS regions12.1and12.2separate adjacent active regions16.1from16and18.1from18, respectively. On the upper surface of the LOCOS regions12.1, 12.2are polysilicon tiles14.1, 14.2, respectively. At the corner of the gate polysilicon14.3and the polysilicon tiles14.1and14.2are oxide spacers60.1-60.6. The polysilicon tiles14.1, 14.2have silicide layers50.1, 50.2. Other silicide layers50.4-50.6are on the tops of the source, drain and polysilicon gate. An insulation layer32covers the substrate and metal contacts36, 34, 38extend from the surface of the layer32to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions. In addition, the poly tiles themselves increase the thickness of the isolation between active silicon regions when it must serve as a self-aligned blocking layer for an ion implantation step.
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Hahn Daniel J.
Leibiger Steven
Fairchild Semiconductor Corporation
FitzGerald Esq. Thomas R.
Garber Charles D
Hiscock & Barclay LLP
Isaac Stanetta D
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