Tunable semiconductor diodes

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including passive device

Reexamination Certificate

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C438S379000, C438S383000, C257SE21352

Reexamination Certificate

active

07732293

ABSTRACT:
A diode structure fabrication method. In a P− substrate, an N+ layer is implanted. The N+ layer has an opening whose size affects the breakdown voltage of the diode structure. Upon the N+ layer, an N− layer is formed. Then, a P+ region is formed to serve as an anode of the diode structure. An N+ region can be formed on the surface of the substrate to serve as a cathode of the diode structure. By changing the size of the opening in the N+ layer during fabrication, the breakdown voltage of the diode structure can be changed (tuned) to a desired value.

REFERENCES:
patent: 5223737 (1993-06-01), Canclini
patent: 5426320 (1995-06-01), Zambrano
patent: 5708289 (1998-01-01), Blanchard
patent: 6093620 (2000-07-01), Peltzer
patent: 6507080 (2003-01-01), Jang et al.
patent: 2003/0047750 (2003-03-01), Russ et al.
patent: 2004/0169233 (2004-09-01), Yamamoto et al.
Notice of Allowance (mail date Jun. 6, 2008) for U.S. Appl. No. 11/469,582, filed Sep. 1, 2006; First Named Inventor Steven H. Voldman; Customer No. 30449.
Notice of Allowance (mail date Aug. 1, 2006) for U.S. Appl. No. 10/707,722, filed Jan. 7, 2004; First Named Inventor Steven H. Voldman; Customer No. 30449.

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