Leadframe and mold compound interlock in packaged...

Details Leadframe and mold compound interlock in packaged... Leadframe and mold compound interlock in packaged...

2007-10-18

2010-06-22

Nguyen, Dao H (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With dam or vent for encapsulant

Reexamination Certificate

active

07741704

ABSTRACT:
An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

REFERENCES:
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patent: 6424024 (2002-07-01), Shih et al.
patent: 6483178 (2002-11-01), Chuang
patent: 7411280 (2008-08-01), Yazid et al.
patent: 2003/0015780 (2003-01-01), Kang et al.
patent: 2003/0141577 (2003-07-01), Hung et al.
patent: 2003/0189222 (2003-10-01), Itou et al.
patent: 2004/0207054 (2004-10-01), Brown et al.
patent: 2008/0079127 (2008-04-01), Gerber
patent: 2005017968 (2005-02-01), None

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