Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2008-02-15
2010-06-08
Donovan, Lincoln (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S537000, C363S060000
Reexamination Certificate
active
07733161
ABSTRACT:
A voltage boost system, IC and design structure are disclosed for boosting a supply voltage while preventing forward biasing of n-well structures. The voltage boost system may include a first voltage boost circuit producing a first boosted voltage using at least one voltage boost sub-circuit, each of the at least one voltage boost sub-circuit having an output passgate in an n-well; a second voltage boost circuit producing a second boosted voltage, the n-well of each output passgate being biased using the second boosted voltage, wherein the second boosted voltage is greater than the first boosted voltage. Voltage boost sub-circuits may use gate control circuitry to reduce gate oxide stress, thus allowing lower voltage level FETs to be used.
REFERENCES:
patent: 4616303 (1986-10-01), Mauthe
patent: 5059815 (1991-10-01), Bill et al.
patent: 5066870 (1991-11-01), Kobatake
patent: 5886566 (1999-03-01), Park et al.
patent: 6072358 (2000-06-01), Hung et al.
patent: 6163487 (2000-12-01), Ghilardelli
patent: 6236581 (2001-05-01), Foss et al.
patent: 6466079 (2002-10-01), Kushnarenko
patent: 6724240 (2004-04-01), Egerer
patent: 6734717 (2004-05-01), Min
patent: 7046076 (2006-05-01), Daga et al.
patent: 7075357 (2006-07-01), Koshita
patent: 7256640 (2007-08-01), Ucciardello et al.
patent: 7403054 (2008-07-01), Malladi et al.
patent: 7466188 (2008-12-01), Fifield
Ker et al., “Design of Charge Pump Circuit With Consideration of Gate-Oxide Reliability in Low-Voltage CMOS Processes”, IEEE Journal of Solid-State Circuits, vol. 41, No. 5, May 2006, pp. 1100-1107.
Hasan et al., “A 5V Charge Pump in a Standard 1.8V 0.18-um CMOS Process”, IEEE, 2005, pp. 1899-1902.
Su et al., “Gate Control Stategies for High Efficiency Charge Pumps”, IEEE, 2005, pp. 1907-1910.
Ker et al., “A New Charge Pump Circuit Dealing with Gate-Oxide Reliability Issue in Low-Voltage Processes”, IEEE Journal of Solid State Circuits, ISCAS 2004, pp. I-321-I-324.
Min et al., “CMOS Charge Pumps Using Cross-Coupled Charge Transfer Switches with Improved Voltage Pumping Gain and Low Gate-Oxide Stress for Low-Voltage Memory Circuits”, IEEE, 2002, pp. V-545-V-548.
Dreibelbis et al., U.S. Appl. No. 12/031,731, Office Action Communication, Sep. 3, 2009, 13 pages.
Dreibelbis et al., U.S. Appl. No. 12/031,725, Office Action Communication, Sep. 8, 2009, 17 pages.
Dreibelbis Jeffrey H.
Fifield John A.
Donovan Lincoln
Englund Terry L
Harding W. Riyon
Hoffman Warnick LLC
International Business Machines - Corporation
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