Algebraic single instruction multiple data processing

Electrical computers and digital processing systems: processing – Processing architecture – Array processor

Reexamination Certificate

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Details

C712S220000

Reexamination Certificate

active

07814297

ABSTRACT:
A data processing apparatus comprises data processing logic operable to perform data processing operations specified by program instructions. The data processing logic (140) has a plurality of functional units (142, 144, 146) configured to execute in parallel on data received from a data source. A decoder (130) is responsive to a single program instruction to control the data processing logic (140) to concurrently execute the single program instruction on each of a plurality of vector elements of each of a respective plurality of vector input operands (310, 320) received from the data source using the plurality of functional units (142, 144, 146). During execution of the single program instruction, the plurality of functional units (142, 144, 146) operate as a predetermined group on said plurality of vector elements (310, 320) to perform at least a matrix-vector calculation in which the matrix is a non-identity matrix and entries of the matrix are one of:(i) populated in dependence upon at least one of said vector elements of at least one of the plurality of vector input operands; and(ii) generated within said data processing logic as an explicit function of the single program instruction.

REFERENCES:
patent: 5099448 (1992-03-01), Myers et al.
patent: 5175862 (1992-12-01), Phelps et al.
patent: 5319586 (1994-06-01), Gupta et al.
patent: 6397235 (2002-05-01), Van Eijndhoven et al.
patent: 6944747 (2005-09-01), Nair et al.

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