High performance clock system error detection and fault isolatio

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G06F 1100

Patent

active

048005649

ABSTRACT:
A method and apparatus for fault testing a clock distribution network for A.C. and D.C. faults. The fault testing apparatus includes test latch circuit means and is adapted to initially test for D.C. (stuck) faults and to thereafter continuously monitor a plurality of clock signal lines to detect A.C. clock faults.

REFERENCES:
patent: 3056108 (1962-09-01), Heineck
patent: 4081662 (1978-03-01), Pehrson
patent: 4144448 (1979-03-01), Pisiotta
patent: 4392226 (1983-07-01), Cook
patent: 4441075 (1984-04-01), McMahon
patent: 4542509 (1985-09-01), Buchanan
patent: 4683570 (1987-07-01), Bedard
patent: 4686677 (1987-08-01), Flora

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