Power supply voltage drop detection circuit for use in EEPROM me

Details Power supply voltage drop detection circuit for use in EEPROM me Power supply voltage drop detection circuit for use in EEPROM me

1989-11-30

1991-04-16

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307310, 307362, 365228, H03K 5153, H03K 301

Patent

active

050085662

ABSTRACT:
A power supply voltage drop detection circuit has first and second N-channel field-effect-transistors. The drain of the first N-channel FET is connected to a power supply voltage line and its gate to ground. The drain of the second N-channel FET connected to the source of the first N-channel FET and its source is connected to the ground. A control voltage to the gate of the second N-channel FET maintains the second N-channel FET conducting. A P-channel field-effect-transistor has its source connected to the power supply voltage line and its gate connected to a connection node between the first and second N-channel field-effect-transistors. A third N-channel FET has its drain connected to the drain of the P-channel FET and its source connected to the ground. The gate of the third N-channel FET receives a controlled gate voltage which maintains the third N-channel FET conducting. An inverter has its input connected to a node between the P-channel FET and the third N-channel FET. The inverter output generates a signal indicative of the power supply voltage drop.

REFERENCES:
patent: 4293782 (1981-10-01), Tanaka et al.
patent: 4649292 (1987-03-01), Rusznyak
patent: 4658156 (1987-04-01), Hashimoto
patent: 4716323 (1987-12-01), Wada et al.
patent: 4717840 (1988-01-01), Ouyang et al.
patent: 4760284 (1988-07-01), Taylor
patent: 4812679 (1989-03-01), Mahabadi
patent: 4874965 (1989-10-01), Campardo et al.

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