PLL circuit with improved phase difference detection

Details PLL circuit with improved phase difference detection PLL circuit with improved phase difference detection

2008-04-29

2010-12-28

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000, C331S034000, C331S17700V, C327S156000, C375S376000

Reexamination Certificate

active

07859344

ABSTRACT:
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.

REFERENCES:
patent: 7123102 (2006-10-01), Uozumi et al.
patent: 7425874 (2008-09-01), Risbo et al.
patent: 2005/0116258 (2005-06-01), Yamagishi et al.
ISSCC 2004/Session 26/Optical and Fast I/0 /26.10, Lin, et al., “A PVT Tolerant O.18MHz to 600 MHz Self-Calibrated Digital PLL in 90nm CMOS Process”.
IEEE Journal of Solid-State Circuits, vol. 39, No. 5, May 2004, “A Digitally Controlled PLL for SoC Applications” Olson, et al.
IEEE Journal of Solid-State Circuits, vol. 38, No. 2, Feb. 2003, “An ALL-Digital PLL for Frequency Multiplication by 4 to 1022 With Seven-Cycle Lock Time” by Watanabe, et al.
IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 41, No. 5, May 1994., “A Simplified Continuous Phase Modulator Technique” T. Riley, et al.

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