Stud bumps as local heat sinks during transient power...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents

Reexamination Certificate

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C257S706000, C257S712000, C257S713000, C257S717000, C257S718000, C257SE21497, C257SE21499, C257SE21508, C257SE21514, C361S688000, C361S704000, C361S705000, C361S707000

Reexamination Certificate

active

07838988

ABSTRACT:
A thermal management configuration for a flip chip semiconductor device is disclosed. The device includes a high power silicon based die having a metal bonding surface. A plurality of interconnects are formed on the metal surface and connected to a substrate. A plurality of thermal management stud bumps are formed on the metal bonding surface, the thermal management stud bumps positioned distinct from the interconnects and local to die hot spots, exposed ends of the thermal management stud bumps spaced from the substrate.

REFERENCES:
patent: 4764804 (1988-08-01), Sahara et al.
patent: 7566590 (2009-07-01), Zhong et al.
patent: 2006/0237839 (2006-10-01), Akram et al.
patent: 2008/0164603 (2008-07-01), Sturcken et al.
patent: 2008/0265385 (2008-10-01), Tsai et al.

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