Offset voltage correction circuit and class D amplifier

Details Offset voltage correction circuit and class D amplifier Offset voltage correction circuit and class D amplifier

2007-07-06

2010-10-19

Pascal, Robert (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including plural stages cascaded

C330S260000

Reexamination Certificate

active

07816992

ABSTRACT:
An offset voltage correction circuit for a differential amplifier comprising NMOS transistors serving as a pair of differential transistors, and PMOS transistors serving as a pair of load transistors connected between outputs of the pair of differential transistors and a power source. The offset voltage correction circuit is equipped with a voltage generator for generating, between a source of any one of the pair of load transistors and the power source, a constant voltage for correcting an offset voltage of the differential amplifier.

REFERENCES:
patent: 4717888 (1988-01-01), Vinn et al.
patent: 4806875 (1989-02-01), Schaffer
patent: 5061900 (1991-10-01), Vinn et al.
patent: 5548241 (1996-08-01), McClure
patent: 5550512 (1996-08-01), Fukahori
patent: 5812005 (1998-09-01), Ezell et al.
patent: 6114907 (2000-09-01), Sakurai
patent: 7095275 (2006-08-01), Miyazaki
patent: 7167046 (2007-01-01), Maejima
patent: 59-144209 (1984-08-01), None
patent: 02-185106 (1990-07-01), None
patent: 6-41382 (1994-10-01), None
patent: 08-037430 (1996-06-01), None
patent: 09-246885 (1997-09-01), None
patent: 2000-183671 (2000-06-01), None
patent: 2004120102 (2004-04-01), None
patent: 2004527179 (2004-09-01), None
patent: 2006042296 (2006-02-01), None
patent: 20050001317 (2005-01-01), None
patent: WO 02/087073 (2002-10-01), None
Japanese Patent Office: Notification of Reasons for Refusal for Patent Application No. 2006-188624 (Drafting Date: Jan. 20, 2009).
Korean Patent Office: Notice of Preliminary Rejection for Patent Application No. 10-2007-0068310 (Issued: Sep. 29, 2008).
Japanese Patent Office: “Office Action”, Notification of Reason for Refusal for Patent Application No. 2006-188657 (Issued: Jul. 8, 2008).
Japanese Patent Office, “Notification of Reason for Refusal,” (Jun. 10, 2008).
Japanese Patent Office: Notification of Reasons for Refusal for Patent Application No. 2006-188624 (Drafting Date: Sep. 11, 2009).
Japanese Patent Office “Notification of Reasons for Refusal”, Japanese Patent Application No. 2006-188624, Drafting Date Jun. 14, 2010, 6 pages.

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