Register controlled delay locked loop circuit

Details Register controlled delay locked loop circuit Register controlled delay locked loop circuit

2008-06-30

2010-06-15

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S149000

Reexamination Certificate

active

07737744

ABSTRACT:
A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a clock edge of the source clock in response to an output signal of the phase comparator. The clock delay circuit delays the phase of the internal clock using first delay units for a predetermined delay duration, and thereafter delays the phase of the internal clock using second delay units, the second delay unit providing a longer delay than the first delay unit. A delay replica model is configured to reflect actual delay conditions of the source clock in an output clock of the clock delay circuit to output the feedback clock.

REFERENCES:
patent: 6727738 (2004-04-01), Tsukikawa
patent: 7358784 (2008-04-01), Kim et al.
patent: 2003/0076143 (2003-04-01), Nishimura et al.
patent: 2008/0079470 (2008-04-01), Yun et al.
patent: 1020030052651 (2003-06-01), None
patent: 1020040093819 (2004-11-01), None
patent: 1020040098899 (2004-11-01), None
patent: 1020040103035 (2004-12-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Aug. 26, 2009 with an English Translation.

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