Universal and fault-tolerant multiphase digital PWM...

Coded data generation or conversion – Digital code to digital code converters

Reexamination Certificate

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C375S238000

Reexamination Certificate

active

07667625

ABSTRACT:
A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The unclocked logic can include a delay line.

REFERENCES:
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patent: 6833691 (2004-12-01), Chapuis
patent: 7459951 (2008-12-01), Prodic
patent: 2005/0135023 (2005-06-01), Goder et al.
patent: 2006/0022656 (2006-02-01), Leung et al.
patent: WO 2006/037214 (2006-04-01), None
Vahid Yousefzadeh,Toru Takayama,Dragan Maksimovie, Hybrid DPWM with Digital Delay Locked Loop, IEEE COMPEL Workshop, Jul. 16-19, 2006.
Raymond Foley, Richard Kavanagh, William Marnane, Multiphase Digital Delay Locked Loop, IEEE, vol. 21, No. 3 May 2006.
U.S. International Searching Authority, International Search Report and Written Opinion for International Appln. No. PCT/2008/055028, dated Oct. 14, 2009, 11 pages.

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