Semiconductor package substrate structure and manufacturing...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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C257S780000, C257S781000, C257S741000, C257S750000

Reexamination Certificate

active

07847400

ABSTRACT:
A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

REFERENCES:
patent: 6001493 (1999-12-01), Rutledge et al.
patent: 7078272 (2006-07-01), Ho et al.
patent: 2003/0022477 (2003-01-01), Hsieh et al.
patent: 2006/0226544 (2006-10-01), Hsu et al.

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