System and method for providing a robust ultra low power...

Details System and method for providing a robust ultra low power... System and method for providing a robust ultra low power...

2005-03-31

2010-06-01

Payne, David C (Department: 2611)

Pulse or digital communications

Synchronizers

C327S141000, C358S409000, C370S503000, C713S400000, C714S012000

Reexamination Certificate

active

07729459

ABSTRACT:
A system and method is disclosed for providing a robust ultra low power serial interface with a digital clock and data recovery circuit for power management systems. In one advantageous embodiment a digital clock and data recovery circuit of the invention comprises a quadruple phase clock generator circuit that generates four shifted clock signals, a decision logic circuit, a state detector circuit, and an edge detector circuit. The detected edges of data signals are used to latch the state of the four shifted clock signals. The state detector circuit selects a stable clock signal among the four shifted clock signals for use as a recovered clock signal and synchronizes the recovered clock signal at a center of the data signal. The selected recovered clock signal remains available until another data signal transition is detected.

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