Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2006-02-27

2010-12-07

Smith, Bradley K (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

C438S135000

Reexamination Certificate

active

07847321

ABSTRACT:
A semiconductor device includes a field effect transistor and a strain generating layer to apply a stress to a channel region of the field effect transistor. The strain generating layer contains at least one of oxygen and nitrogen of 1.0×1018cm−3to 5.0×1019cm−3, or alternatively, the strain generating layer contains self-interstitial atoms and/or vacancies of 1.0×1018cm−3to 5.0×1019cm−3. In the latter case, at least a portion of the self-interstitial atoms and/or the vacancies exist as a cluster.

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A Shimizu et al.; “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, IEEE, 2001. (Discussed in the specification).
K. Goto et al.; “Technology Booster using Strain-Enhancing Laminated SiN (SELS) for 65nm Node HP MPUs”, IEEE, 2004. (Discussed in the specification).
“Research Report on Control of Material Function Utilizing Semiconductor Lattice Defect”; The Society of Non-Traditional Technology, pp. 72-74, 1986. (Discussed in the specification).

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