Manufacturing method of high voltage semiconductor device...

Details Manufacturing method of high voltage semiconductor device... Manufacturing method of high voltage semiconductor device...

2007-10-04

2010-02-09

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S424000, C438S527000, C257SE21639

Reexamination Certificate

active

07659177

ABSTRACT:
Disclosed is a semiconductor device, and more particularly, a manufacturing method of a high voltage semiconductor device. The method includes: forming a semiconductor substrate having a key area for an alignment key, a low voltage area for a low voltage device, and a high voltage area for a high voltage device; forming an oxide film on the substrate; and forming an insulating film on the oxide film. After removing the insulating film, the method includes forming a plurality of shallow trench isolations (STI's) in the areas of the substrate; forming a nitride layer on the substrate and on STIs; sequentially forming a plurality of wells and drift areas by implanting an impurity ion into the high voltage area; and sequentially forming the plurality of wells and the drift areas by implanting an impurity ion into the low voltage area. A system on chip (SOC) process may thus be simplified.

REFERENCES:
patent: 6451640 (2002-09-01), Ichikawa
patent: 6514810 (2003-02-01), Kim et al.
patent: 7205630 (2007-04-01), Chang et al.
patent: 7414292 (2008-08-01), Ema et al.
patent: 2005/0087810 (2005-04-01), Sadra et al.
patent: 2006/0118854 (2006-06-01), Lee
patent: 2007/0066087 (2007-03-01), Jung

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