Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-08-27
2010-12-28
Dinh, Duc Q (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000
Reexamination Certificate
active
07859510
ABSTRACT:
A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.
REFERENCES:
patent: 5222082 (1993-06-01), Plus
patent: 5434899 (1995-07-01), Huq et al.
patent: 5708455 (1998-01-01), Maekawa
patent: 6052426 (2000-04-01), Maurice
patent: 6300928 (2001-10-01), Kim
patent: 6426743 (2002-07-01), Yeo et al.
patent: 6556646 (2003-04-01), Yeo et al.
patent: 6664943 (2003-12-01), Nakajima et al.
patent: 6724361 (2004-04-01), Washio et al.
patent: 6789514 (2004-09-01), Suh et al.
patent: 6813332 (2004-11-01), Nagao et al.
patent: 6919874 (2005-07-01), Maurice
patent: 6928136 (2005-08-01), Nagao et al.
patent: 7042430 (2006-05-01), Isami et al.
patent: 7190342 (2007-03-01), Matsuda et al.
patent: 7274351 (2007-09-01), Washio et al.
patent: 7369113 (2008-05-01), Washio et al.
patent: 7486269 (2009-02-01), Moon
patent: 7538753 (2009-05-01), Tanada
patent: 2002/0044111 (2002-04-01), Yamazaki et al.
patent: 2003/0052848 (2003-03-01), Yamaguchi
patent: 2004/0046729 (2004-03-01), Moon
patent: 2005/0008114 (2005-01-01), Moon
patent: 2006/0001637 (2006-01-01), Pak et al.
patent: 2006/0001638 (2006-01-01), Jeon et al.
patent: 2006/0145998 (2006-07-01), Cho et al.
patent: 2010/0026619 (2010-02-01), Umezaki
patent: 2360651 (2001-09-01), None
patent: 10-500243 (1998-01-01), None
Jae Hwan Oh et al.; “15.2: 2.0 inch a-Si:H TFT-LCD with Low Noise Integrated Gate Driver”;SID '05 Digest; pp. 942-945; 2005.
Hsi-Rong Han et al.; “15.3: Reliable Integrated a-Si Select Line Driver for 2.2-in. QVGA TFT-LCD”;SID '05 Digest; pp. 946-949; 2005.
Search Report (European Patent Application No. 07016494.2) dated Jul. 16, 2009.
Dinh Duc Q
Fish & Richardson P.C.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Liquid crystal display device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Liquid crystal display device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Liquid crystal display device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4190154