SerDes double rate bitline with interlock to block precharge...

Details SerDes double rate bitline with interlock to block precharge... SerDes double rate bitline with interlock to block precharge...

2008-10-29

2010-11-23

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S203000, C365S189050

Reexamination Certificate

active

07839715

ABSTRACT:
An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.

REFERENCES:
patent: 5909394 (1999-06-01), Chou
patent: 6850460 (2005-02-01), Chan et al.
patent: 6891774 (2005-05-01), Abdollahi-Alibeik et al.
patent: 7158412 (2007-01-01), Rodgers, III

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