Method of erasing a nonvolatile memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185220, C365S203000

Reexamination Certificate

active

07738303

ABSTRACT:
The present invention relates to a method of erasing a nonvolatile memory device. According to an aspect of the present invention, an erase operation is performed on a selected memory block. The bit lines of the memory block are precharged, and a change of a voltage level of the bit lines is verified according to an erase state of the memory cells. A data read operation is performed on a first bit line according to a voltage level of the first bit line. A data read operation is performed on a second bit line according to a voltage level of the second bit line. The data read operation is performed on the second bit line after the data read operation is performed on the first bit line. An erase verify result is then determined according to the data read operation result.

REFERENCES:
patent: 7460410 (2008-12-01), Nagai et al.
patent: 1020060070030 (2006-06-01), None
patent: 1020080007553 (2008-01-01), None

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