Glitch-free clock regeneration circuit

Details Glitch-free clock regeneration circuit Glitch-free clock regeneration circuit

2007-02-28

2010-02-09

Lam, Tuan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S144000, C327S146000

Reexamination Certificate

active

07659757

ABSTRACT:
A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.

REFERENCES:
patent: 6222392 (2001-04-01), Guo et al.
patent: 6310653 (2001-10-01), Malcolm et al.
patent: 2008/0116964 (2008-05-01), Kernahan et al.

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