Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2008-08-18
2010-02-02
Cox, Cassandra (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S157000
Reexamination Certificate
active
07656223
ABSTRACT:
The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback clock signal falling within less than 180 degrees from the first edge, switching on of a switching transistor of source current and switching off of the switching transistor of sink current; and iii) following detection of an edge of another reference signal at a point in time about midway between the first edge and a next similar edge of the reference clock signal has past, switching off of the switching transistor of source current while maintaining the switching transistor of sink current switched off.
REFERENCES:
patent: 4792705 (1988-12-01), Ouyang et al.
patent: 5465388 (1995-11-01), Zicker
patent: 5734279 (1998-03-01), Bereza
patent: 5966033 (1999-10-01), Miller
patent: 6271729 (2001-08-01), Sung et al.
patent: 6304116 (2001-10-01), Yoon et al.
patent: 6393284 (2002-05-01), Dent
patent: 6407601 (2002-06-01), Lin
patent: 6472914 (2002-10-01), Gu et al.
patent: 6483389 (2002-11-01), Lamb
patent: 6525684 (2003-02-01), Tsujikawa
patent: 6646478 (2003-11-01), Lamb
patent: 6717446 (2004-04-01), Vu
patent: 6724265 (2004-04-01), Humphreys
patent: 6774689 (2004-08-01), Sudjian
patent: 6876240 (2005-04-01), Moon et al.
patent: 6897690 (2005-05-01), Keaveney et al.
patent: 6906565 (2005-06-01), Keaveney
patent: 6952462 (2005-10-01), Harrison
patent: 6958636 (2005-10-01), Boerstler et al.
patent: 6975840 (2005-12-01), Lin
patent: 6989698 (2006-01-01), Jeong
patent: 6995607 (2006-02-01), Dosho et al.
patent: 7271621 (2007-09-01), Metz
patent: 7443250 (2008-10-01), Seethamraju et al.
patent: 7511543 (2009-03-01), Friedman et al.
patent: 2006/0170471 (2006-08-01), Haerle et al.
U.S. Appl. No. 11/691,849, Notice of Allowance dated Dec. 24, 2008.
U.S. Appl. No. 11/691,849, Office Action dated Jun. 6, 2008.
Kim et al., “A 64-MByte/s Bidirectional Data Strobed, Double-Data-Rate SDRAM with a 40-mW DLL for a 256-MByte Memory System”, IEEE Journal of Solid-State Circuits, vol. 33(11), Nov. 1998, pp. 1703-1710.
Moon et al., “An All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide Range Operation and Low-Jitter Performance”, IEEE Journal of Solid-State Circuits, vol. 35(3), Mar. 2000, pp. 377-384.
Borden Ladner Gervais LLP
Cox Cassandra
Hung Shin
MOSAID Technologies Incorporated
LandOfFree
Delay locked loop circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Delay locked loop circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay locked loop circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4171838