High speed, low power, multi-bit, single edge-triggered, wraparo

Details High speed, low power, multi-bit, single edge-triggered, wraparo High speed, low power, multi-bit, single edge-triggered, wraparo

1985-09-30

1987-10-13

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Particular input circuit

377 41, 377107, 377111, 377117, 377121, 377105, H03K 2344, H03K 2102

Patent

active

047003707

ABSTRACT:
A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state. Counter-update gating devices are interconnected between a counter pulse signal and each of the counter cells so as to determine which of the counter cells are to receive the counter-update signal so as to change the state of the true and complement addresses.

REFERENCES:
patent: 3745372 (1973-07-01), Koster
patent: 3766408 (1973-10-01), Suzuki et al.
patent: 3943378 (1976-03-01), Beutler
patent: 4182961 (1980-01-01), Dingwall
patent: 4218750 (1980-08-01), Carter et al.
patent: 4512030 (1985-04-01), Fukuta

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