Method of manufacturing electronic component package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C029S843000

Reexamination Certificate

active

07816176

ABSTRACT:
In a method of manufacturing an electronic component package, first, a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages are formed by plating on a top surface of a substrate to thereby fabricate a wafer. The wafer includes a plurality of pre-base portions that will be separated from one another later to become bases of the respective electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chip are connected to the external connecting terminals. Next, the electronic component chip is sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.

REFERENCES:
patent: 3489952 (1970-01-01), Hinchey
patent: 5926380 (1999-07-01), Kim
patent: 6746897 (2004-06-01), Fukutomi et al.
patent: 2003/0207495 (2003-11-01), Akram
patent: A-2001-035993 (2001-02-01), None
patent: A-2001-244403 (2001-09-01), None
U.S. Appl. No. 11/706,367, filed on Feb. 15, 2007 in the name of Yoshitaka Sasaki et al.

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