Stacked semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S723000, C257S777000, C257SE23013

Reexamination Certificate

active

07808093

ABSTRACT:
A stacked semiconductor device is constructed by stacking in two levels: a lower semiconductor device having a wiring board, at least one semiconductor chip mounted on a first surface of the wiring board and having electrodes electrically connected to wiring by way of a connection means, an encapsulant composed of insulating plastic that covers the semiconductor chip and the connection means, a plurality of electrodes formed overlying the wiring of a second surface of the wiring board, and a plurality of linking interconnects each having a portion connected to the wiring of the first surface of the wiring board and another portion exposed on the surface of the encapsulant; and an upper semiconductor device in which each electrode overlies and is electrically connected to the exposed portions of each of the linking interconnects of the lower semiconductor device. The linking interconnects extend from the first surface of the wiring board to the side surfaces and upper surface of the encapsulant, and moreover, electrically connect with wiring of the wiring board that projects from the encapsulant.

REFERENCES:
patent: 7550857 (2009-06-01), Longo et al.
patent: 2006/0128062 (2006-06-01), Doescher
patent: 2007/0045796 (2007-03-01), Ye et al.
patent: 2007/0096291 (2007-05-01), Kawabata et al.
patent: 2007/0155048 (2007-07-01), Lee et al.
patent: 2004-172157 (2004-06-01), None
patent: 2004-273938 (2004-09-01), None

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