Semiconductor memory device and method for operating the same

Details Semiconductor memory device and method for operating the same Semiconductor memory device and method for operating the same

2008-06-30

2010-10-12

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233100

Reexamination Certificate

active

07813217

ABSTRACT:
A semiconductor memory device is capable of generating a desired output enable signal without increasing an initial count value and bit number and generating a desired final output enable signal, without unnecessary reset operations, by reflecting column address strobe (CAS) latency information on an external clock count value. The semiconductor memory device includes a first output enable signal generating unit and a final output enable signal generating unit. The first output enable signal generating unit is configured to compare a first count value, which is obtained by counting a delay locked loop (DLL) clock, to a second clock count value, which is obtained by counting an external clock until a read command is input, and to output a first output enable signal. The final output enable signal generating unit is configured to output a final output enable signal generated by shifting the first output enable signal, according to CAS latency.

REFERENCES:
patent: 7342412 (2008-03-01), Kim
patent: 2003/0218921 (2003-11-01), Schrogmeier et al.
patent: 2006/0145894 (2006-07-01), Kim et al.
patent: 2007/0126468 (2007-06-01), Kim
patent: 2009/0274001 (2009-11-01), Jeong
patent: 1020060077551 (2006-07-01), None
patent: 1020070098038 (2007-10-01), None

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