Logic entity with two outputs for efficient adder and other...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07617269

ABSTRACT:
An improved logic entity with two outputs for efficient adder and other macro implementations providing fast response with reduced area requirements, comprising a first lookup table for generating a first output for the carry out value for a carry-in of zero and a second output for the sum value for a carry-in of one; a second lookup table for generating a first output for the carry out value for a carry-in of one and a second output for the sum value for a carry-in of zero; a first multiplexer is connected to a first input from the first output of the first lookup table and a second input from the first output of the second lookup table; a second multiplexer is connected to a first input from the second output of the first lookup table and a second input from the second output of the second lookup table; thereby, getting two output taps for sum and carry implementation.

REFERENCES:
patent: 5349250 (1994-09-01), New
patent: 5481206 (1996-01-01), New et al.
patent: 5724276 (1998-03-01), Rose et al.
patent: 7218139 (2007-05-01), Young et al.
patent: 7302460 (2007-11-01), Langhammer

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