Dummy load controlled multilevel logic single clock logic circui

Details Dummy load controlled multilevel logic single clock logic circui Dummy load controlled multilevel logic single clock logic circui

1986-10-20

1987-10-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307453, 307468, 307481, 365233, H03K 1728, H03K 1996

Patent

active

047000880

ABSTRACT:
A multi-level logic circuit includes a first plurality of logic circuits that are connected in a cascade arrangement. A second plurality of dummy logic circuits also connected in casacade arrangement are used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source provides a precharged signal to the first plurality of logic circuits and the second plurality of dummy logic circuits and an evaluation circuit is used to combine the clock signal with an output signal from the dummy logic signal to obtain an evaluation signal for evaluating the logic states of the first plurality of logic circuits.

REFERENCES:
patent: 3566153 (1971-02-01), Spencer, Jr.
patent: 3866186 (1975-02-01), Suzuki
patent: 4291247 (1981-09-01), Cooper, Jr. et al.
patent: 4501977 (1985-02-01), Koike

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