Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2005-01-11
2009-12-08
Rose, Kiesha L (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257SE23002
Reexamination Certificate
active
07629689
ABSTRACT:
A semiconductor integrated circuit having connection pads arranged over active elements is disclosed. The connection pad is divided into a probing area and a bonding area, and reinforcing structures are formed separately under the respective areas. The reinforcing structure under the probing area is formed using a number of wiring layers less than the number of wiring layers used for forming the reinforcing structure under the bonding area. As a result, the wiring layers under the probing area are efficiently utilized to forms wires for realizing the logical function of the integrated circuit.
REFERENCES:
patent: 5365091 (1994-11-01), Yamagishi
patent: 5394013 (1995-02-01), Oku
patent: 5751065 (1998-05-01), Chittipeddi et al.
patent: 5986343 (1999-11-01), Chittipeddi et al.
patent: 6008542 (1999-12-01), Takamori
patent: 6022791 (2000-02-01), Cook et al.
patent: 6100589 (2000-08-01), Tanaka
patent: 6143396 (2000-11-01), Saran et al.
patent: 6163075 (2000-12-01), Okushima
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6232662 (2001-05-01), Saran
patent: 6297563 (2001-10-01), Yamaha
patent: 6448650 (2002-09-01), Saran et al.
patent: 6489228 (2002-12-01), Vigna et al.
patent: 6495917 (2002-12-01), Ellis-Monaghan et al.
patent: 6559548 (2003-05-01), Matsunaga et al.
patent: 6586839 (2003-07-01), Chisholm et al.
patent: 6614091 (2003-09-01), Downey et al.
patent: 6731007 (2004-05-01), Saito et al.
patent: 6762499 (2004-07-01), Nakadaira
patent: 6803302 (2004-10-01), Pozder et al.
patent: 6822329 (2004-11-01), Varrot et al.
patent: 6881597 (2005-04-01), Asayama et al.
patent: 6890828 (2005-05-01), Horak et al.
patent: 6921979 (2005-07-01), Downey et al.
patent: 7015588 (2006-03-01), Komatsu
patent: 7038280 (2006-05-01), Righter
patent: 7071575 (2006-07-01), Wu et al.
patent: 7091613 (2006-08-01), Long et al.
patent: 7115985 (2006-10-01), Antol et al.
patent: 7157734 (2007-01-01), Tsao et al.
patent: 2003/0168748 (2003-09-01), Katagiri et al.
patent: 2003/0230809 (2003-12-01), Nakajima et al.
patent: 2004/0016949 (2004-01-01), Semi
patent: 2004/0150112 (2004-08-01), Oda
patent: 2005/0167842 (2005-08-01), Nakamura et al.
patent: A-11-307724 (1999-11-01), None
patent: A-2000-164620 (2000-06-01), None
patent: A-2001-7113 (2001-01-01), None
patent: A-2002-16069 (2002-01-01), None
patent: A-2002-76075 (2002-03-01), None
patent: A-2002-319587 (2002-10-01), None
patent: A-2002-329742 (2002-11-01), None
W. Anderson et al., “ESD Protection Under Wire Bonding Pads”, 1999 EOS/ESD Symposium, pp. 88-94.
L. Mercado et al., “Reliability of Multi-layer Aluminum Capped Copper Interconnect Structures”, 2000 International Electronics Manufacturing Technology Symposium, pp. 84-94.
K-Y. Chou et al., “ESD Protection Under Grounded-Up Bond Pads in 0.13 μm Eight-Level Copper Metal, Fluorinated Silicate Glass Low-k Intermetal Dielectric CMOS Process Technology”, IEEE Electron Device Letters, vol. 22, No. 7, Jul. 2001, pp. 342-344.
K-Y. Chou et al., Active Devices Under CMOS I/O Pads, IEEE Trans Electron Devices, vol. 49, No. 12, Dec. 2002, pp. 2279-2287.
M-D. Ker et al.., “Test Structure and Verification on the MOSFET Under Bond Pad for Area-efficient I/O Layout in High-pin-count SOC IC's”, 2003 IEE International Conference on Microelectronic Test Structures, pp. 161-166.
K. J. Hess et al., Reliability of Bond Over Active Pad Structure for 0.13 -μm CMOS Technology, 2003 Electronic Components and Technology Conference, pp. 1344-1349.
Y. Liu, Thermosonic Wire Bonding Process Simulation and Bond Pad Over Active Stress Analysis, 2004 Electronic Components and Technology Conference, pp. 383-391.
Anya Igwe U
Kawasaki Microelectronics Inc.
Oliff & Berridg,e PLC
Rose Kiesha L
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