Optimizing mode register set commands

Details Optimizing mode register set commands Optimizing mode register set commands

2007-10-30

2009-12-01

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C365S193000, C710S305000

Reexamination Certificate

active

07626884

ABSTRACT:
In one embodiment, the present invention includes a method for generating a mode register set (MRS) decoded signal to identify presence of a MRS command in the register device of a registered DIMM memory, delaying the MRS decoded signal for a predetermined delay and disabling address inversion using the delayed MRS decoded signal, switching from a first command timing frequency to a second command timing frequency for a predetermined number of clock cycles, performing a MRS command to a mode register of the DRAM device, and switching back to the first command timing frequency.

REFERENCES:
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 6385127 (2002-05-01), Ikeda
patent: 7188208 (2007-03-01), David et al.
patent: 2006/0133188 (2006-06-01), Ha et al.

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