Packaging for high speed integrated circuits

Details Packaging for high speed integrated circuits Packaging for high speed integrated circuits

Filed on

2006-06-23

Date issued

2009-12-29

Examiner

Chambliss, Alonzo (Department: 2892)

Patent Class

Active solid-state devices (e.g., transistors, solid-state diode

SubClass

Housing or package

SubSubClass

With contact or lead

Other Related Categories

C257S776000, C257S784000, C257SE23046, C257SE23152, C438S123000, C438S129000

Type

Reexamination Certificate

Status

active

Patent number

07638870

Description

ABSTRACT:
An integrated circuit package comprises an integrated circuit die comprising N adjacent pads, where N is an integer greater than three. A substrate comprises a first pair of traces including first and second traces and a second pair of traces including third and fourth traces. The first, second, third and fourth traces include first ends spaced from the integrated circuit die and second ends adjacent to the integrated circuit die. The first and second pairs of traces carry differential signals. The third trace of the second pair of traces has a first polarity and the fourth trace of the second pair of traces has a second polarity. The third trace is located on one side of the fourth trace at the first end and is located on an opposite side of the fourth trace at the second end. N connections independently connect the second ends to N pads.

REFERENCES:
patent: 3757028 (1973-09-01), Schlessel
patent: 5039824 (1991-08-01), Takashima et al.
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5340771 (1994-08-01), Rostoker
patent: 5430247 (1995-07-01), Bockelman
patent: 5457340 (1995-10-01), Templeton et al.
patent: 5646368 (1997-07-01), Muyshondt et al.
patent: 5646451 (1997-07-01), Freyman et al.
patent: 5650659 (1997-07-01), Mostafazadeh et al.
patent: 5871655 (1999-02-01), Lee et al.
patent: 6317325 (2001-11-01), Patel et al.
patent: 6373740 (2002-04-01), Forbes et al.
patent: 6462404 (2002-10-01), Schoenfeld
patent: 6538336 (2003-03-01), Secker et al.
patent: 6567413 (2003-05-01), Denton et al.
patent: 6649832 (2003-11-01), Brophy et al.
patent: 6747341 (2004-06-01), Knapp et al.
patent: 6812580 (2004-11-01), Wenzel et al.
patent: 6992377 (2006-01-01), Zhou et al.
patent: 7049694 (2006-05-01), Zhou et al.
patent: 7271985 (2007-09-01), Buhler et al.
patent: 7420286 (2008-09-01), Kramer
patent: 2002/0140112 (2002-10-01), Pon
patent: 2003/0110339 (2003-06-01), Calvignac et al.
patent: 2003/0220018 (2003-11-01), Winings et al.
patent: 2004/0000702 (2004-01-01), Knapp et al.
patent: 2005/0017352 (2005-01-01), Lee
patent: 2005/0121766 (2005-06-01), Devnani et al.
patent: 2005/0189643 (2005-09-01), Zhou et al.
patent: 2006/0113665 (2006-06-01), Lee et al.
patent: 2008/0116988 (2008-05-01), Blair et al.
patent: 2008/0258315 (2008-10-01), Okuma
patent: 60 018944 (1985-01-01), None
patent: 62 140446 (1987-06-01), None
patent: 04-091463 (1992-03-01), None
patent: 04-094569 (1992-03-01), None
patent: 05 235245 (1993-09-01), None
patent: 06-177312 (1994-06-01), None
patent: 08-070090 (1996-03-01), None
patent: 2003-068780 (2003-03-01), None
patent: WO 95/06946 (1995-03-01), None
IC Packaging Catalot 2001; Advanced Semiconductor Engineering, Inc.; 2001; 6 pages.
Official Action including the Search Report and Written Opinion from the Intellectual Property Office of Singapore dated Aug. 10, 2007 for Application No. SG 200604689-0; 11 pages.
Official Action including the Search Report and Written Opinion from the Intellectual Property Office of Singapore dated Aug. 14, 2007 for Application No. SG 200604685-8; 9 pages.
Partial translation of Kikuchi, JP 06177312 A, paragraph [0003].
Machine translation of Kikuchi, JP 06177312 A.
Official Action including the Search Report and Written Opinion from the European Patent Office dated Apr. 21, 2009 for Application No. 06014259.3- 1235/1746649; 11 pages.
Official Communication from the European Patent Office dated Apr. 16, 2009 for Application No. 06014260.1 - 1235/1746650; 6 pages.
Shirai et al, “The Technology for Over 300-pin QFPs,” Electronic Components and Technology Conference, 1992. Proceedings., 42nd, May 1992, pp. 423-428.

Affiliated with

Also associated with

Rating

Packaging for high speed integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packaging for high speed integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packaging for high speed integrated circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4122541