Digital loop circuit for programmable logic device

Details Digital loop circuit for programmable logic device Digital loop circuit for programmable logic device

2007-05-21

2009-12-15

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

07633322

ABSTRACT:
A digital loop circuit—i.e., a phase-locked loop (“PLL”) or delay-locked loop (“DLL”)—having a simplified digital loop filter, is particularly well-suited for a programmable logic device (“PLD”). The loop filter may be a memory (e.g., a shift register) which counts the early/late or up/down signals from a phase detector or phase-frequency detector (“error detector”) and outputs a signal when the count exceeds a threshold. Separate integral and proportional paths of the loop may include chained shift registers, with each outputting a signal only when the previous shift register overflows into it. A digital error detector may respond nonlinearly, with outputs of different bit widths, to different amounts of phase or frequency error.

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