Pseudo master slave capture mechanism for scan elements

Details Pseudo master slave capture mechanism for scan elements Pseudo master slave capture mechanism for scan elements

1992-12-23

1995-09-12

Voeltz, Emanuel T.

Excavating

371 223, 371 251, 371 27, 364490, G01R 313183

Patent

active

054504180

ABSTRACT:
A test circuit and test technique for scan testing integrated circuits includes scan cells or capture scan elements arranged in a pseudo master slave configuration. The testing technique utilizes a first independent scan cell as a master stage and a second independent scan cell as a slave stage for propagating data through the IC. The test circuit and test techniques are highly advantageous because of minimal structural overhead. However, the scan cells must be loaded twice to recover the test data because half of the test data is lost when the data is propagated through the IC. The shift register inputs of one scan cell are generally coupled to shift register outputs of other scan cells. Each scan cell generally only includes one latch element.

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Gallup et al., "Testability Features of the 68040", Paper 33.2, pp. 749, 754-755, 1990 International Test Conference.
International Test Conference Proceedings, 1-3 Sep. 1987, Washington US, pp. 460-470, M. J. Ohletz et al. `Overhead in Scan and Self-Testing Designs`.
IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep. 1980 New York US, pp. 1504-1505, `Use of Independent Error Detection Systems for Field Replaceable Units`.
IBM Technical Disclosure Bulletin, vol. 32, No. 5A, Oct. 1989, New York US, pp. 432-434, `Scanning SRL's Containing L2 Latches Without Losing Data`.

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