Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2008-02-25
2009-11-03
Lee, Calvin (Department: 2892)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C438S095000
Reexamination Certificate
active
07612365
ABSTRACT:
A thin blanket epitaxial layer of SiGe is grown on a silicon substrate to have a biaxial compressive stress in the growth plane. A thin epitaxial layer of silicon is deposited on the SiGe layer, with the SiGe layer having a thickness less than its critical thicknesses. Shallow trenches are subsequently fabricated through the epitaxial layers, so that the strain energy is redistributed such that the compressive strain in the SiGe layer is partially relaxed elastically and a degree of tensile strain is induced to the neighboring layers of silicon. Because this process for inducing tensile strain in a silicon over-layer is elastic in nature, the desired strain may be achieved without formation of misfit dislocations.
REFERENCES:
patent: 4994866 (1991-02-01), Awano
patent: 6406973 (2002-06-01), Lee
patent: 6492216 (2002-12-01), Yeo et al.
patent: 6498359 (2002-12-01), Schmidt et al.
patent: 6600170 (2003-07-01), Xiang
patent: 6881635 (2005-04-01), Chidambarrao et al.
patent: 7019326 (2006-03-01), Cea et al.
patent: 7138310 (2006-11-01), Currie et al.
patent: 2004/0021179 (2004-02-01), Lee et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 2005/0093021 (2005-05-01), Ouyang et al.
patent: 2005/0106792 (2005-05-01), Cea et al.
patent: 2005/0133817 (2005-06-01), Huang et al.
patent: 1 231 643 (2002-08-01), None
patent: 1 231 643 (2004-10-01), None
S.C. Jain, H.E. Maes, K. Pinardi, and I. De Wolf, “Stresses and Strains in Lattice-Mismatched Stripes, Quantum Wires, Quantum Dots, and Substrates in Si Technology”, American Institute of Physics. 79 (11), Jun. 1, 1996.
H. Yin, K.D. Hobart and F.J. Kub, S.R. Shieh and T.S. Duffy, J.C. Sturm, “Strain Partition of Si/SiGe and SiO2/SiGe on Compliant Substrates,” American Institute of Physics, Appl. Phys., Jun. 2, 2003.
A. Fisher and H. Richter, “Elastic Misfit Stress Relaxation in Heteroepitaxial SiGe/Si Mesa Structures,” 1992 American Institute of Physics, Appl. Phys. Lett 61(22), Nov. 30, 1992.
Hirohisa Kawasaki, et al., “Impact of Parasitic Resistance and Silicon Layer Thickness Scaling for Strained-Silicon MOSFETs on Relaxed Si1-xGexVirtual Substrate,”, 2004 IEEE.
PCT Search Report and Written Opinion dated Sep. 28, 2007.
Acorn Technologies, Inc.
Lee Calvin
Orrick Herrington & Sutcliffe LLP
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