Analog correction of a phase-mismatch in high-sample rate...

Details Analog correction of a phase-mismatch in high-sample rate... Analog correction of a phase-mismatch in high-sample rate...

2008-01-16

2009-12-08

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter compensation

C341S155000

Reexamination Certificate

active

07629905

ABSTRACT:
A method of phase mismatch correction in high-sample rate time-interleaved analog-to-digital converters (ADC) is provided. An ADC parallel array has an output signal that is processed by a phase-mismatch detector. The detector drives a clock generator control circuit for the ADC array. The clock generator includes a common mode logic (CML) buffer, a CMOS, a non-overlapping generator, a DAC and a decimating low-pass filter. The CML receives a reference clock signal providing source line control (SLC) to the CMOS, the CMOS provides SLC to the DAC that is controlled by the filter which receives a digital control signal from the phase mismatch detector. The DAC provides a corrected timing input to the CMOS that provides the corrected timing signal to the non-overlap generator, where a delay in the clock path is modified and the signal path is unaltered.

REFERENCES:
patent: 7068195 (2006-06-01), Menkus
patent: 7233270 (2007-06-01), Lin
patent: 7466251 (2008-12-01), Uchino
patent: 2008/0084337 (2008-04-01), Batruni

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