Digital delay element for delay mismatch cancellation in...

Details Digital delay element for delay mismatch cancellation in... Digital delay element for delay mismatch cancellation in...

2004-08-25

2009-08-04

Payne, David C (Department: 2611)

Pulse or digital communications

Transmitters

Antinoise or distortion

Reexamination Certificate

active

07570707

ABSTRACT:
A circuit and method therefor provides programmable digital delay that is produced to introduces a delay in either an envelope or a phase signal path of an RF polar transmitter in order to eliminate the delay mismatch between the two paths. For two signal paths, a faster signal may be delayed by a digital processor or a slower signal may be transmitted early so that signals in the two signal paths arrive at a specified circuit node in synchronization. Timing shift may be implemented in either the envelope signal path or the phase signal path and may be used to reduce or increase the timing of a signal path.

REFERENCES:
patent: 5732107 (1998-03-01), Phillips et al.
patent: 6072364 (2000-06-01), Jeckeln et al.
patent: 6304140 (2001-10-01), Thron et al.
patent: 6304619 (2001-10-01), Citta et al.
patent: 6882217 (2005-04-01), Mueller
patent: 2005/0079835 (2005-04-01), Takabayashi et al.
patent: WO 2004032345 A 1 (2004-04-01), None
Lohita et al., “Power amplifier linearization using cubic spline interpolation”, IEEE 43rd Vehicular Technology Conference, May 18-20, 1993, pp. 676-679.

Affiliated with

Also associated with

Rating

Digital delay element for delay mismatch cancellation in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Digital delay element for delay mismatch cancellation in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digital delay element for delay mismatch cancellation in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4098762