Method for forming contacts of semiconductor device

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices

Reexamination Certificate

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C257SE21579

Reexamination Certificate

active

07622331

ABSTRACT:
A method for forming contacts of a semiconductor device is provided. A diffusion barrier layer, an interlayer insulating layer, and a capping layer are sequentially formed on a lower metal wiring layer. A hard mask layer is formed on the capping layer. A photoresist layer is formed and patterned to form vias. Vias are formed by sequentially etching the hard mask, capping, and interlayer insulating layers using the patterned photoresist layer as an etch mask until the diffusion barrier layer is exposed. A metal layer is deposited in the vias to form contacts. The metal and hard mask layers are removed until the capping layer is exposed. This prevents tapering at top of the capping layer during plasma treatment, thus preventing tungsten bridges that may occur through margins of vias when a CMOS device with a strict design rule is manufactured and improving electrical characteristics and reliability of semiconductor devices.

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patent: 1020060064289 (2006-06-01), None
S. Wolf and R.N. Tauber,“Silicon Processing for the VLSI Era”, 2000, Lattice Press, pp. 207-208; 343-347; 667-669; 795-797; 837-838.
S. A. Campbell, “The Science and Fabrication of Microelectronic Fabrication”, 2001, Oxford University Press, pp. 318-319; 343-347.
M. Naik et al., “Process Integration of Double level Copper- Low k (k=2.8) Interconnect”, May 24-26, 1999, Interconnect Technology 1999, International Conference, pp. 181-183.
C. Hierold, “Intelligent CMOS Sensors”, Jan. 23-27, 2000, Micro Electro Mechanical Systems 2000, MEMS 2000, The 13th Annual Conference, pp. 1-6.
Wolf, Silicon Processing for VLSI Era, 2000, Lattice Press, pp. 207-208, 343-347; 667-669; 795-797; 837-838.
Campbell, “The Science and Engineering of Microelectronic Fabrication”, 2001, Oxford University Press, pp. 318-319; 343-347.
Naik, “Process Integration of Doule Level Copper—Low k (k=2.8) Inerconnect”, May 24-26, 1999.
Hierold, “intelligent CMOS Sensors”, Jan. 23-27, 2000, MEMS 2000, pp. 1-6.

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