Systems and methods for efuse fusing time reduction

Details Systems and methods for efuse fusing time reduction Systems and methods for efuse fusing time reduction

2006-07-28

2009-02-10

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

C326S038000, C365S096000

Reexamination Certificate

active

07489180

ABSTRACT:
Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide semiconductor devices that include a fuse blow circuit. The fuse blow circuit provides two fuse blow outputs. Assertion of one of the fuse blow outputs causes one electronic fuse to blow, and assertion of the other fuse blow output causes another electronic fuse to blow. One of the electronic fuses represents a configuration bit while the other electronic fuse represents an inversion status bit indicating an inversion to be applied to the configuration bit. Both the configuration bit and the inversion status bit are applied to an inverter which operates to invert the configuration bit based at least in part on the inversion status bit.

REFERENCES:
patent: 5311472 (1994-05-01), Ota
patent: 5966339 (1999-10-01), Hsu et al.
patent: 6111798 (2000-08-01), Lee
patent: 6977851 (2005-12-01), Noguchi

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