Leading bit anticipator

Details Leading bit anticipator Leading bit anticipator

1996-02-29

1998-08-25

Elmore, Reba I.

Boots, shoes, and leggings

36478401, 36474811, G06F 700, G06F 738, G06F 750

Patent

active

057989524

ABSTRACT:
Improved and less complicated leading bit anticipation (LBA) for a PKG floating point adder of n-bit 2's complement operands is accomplished by representing de-normalized (n+1)-bit operands as (n+1)-many PKG symbols. These are grouped into (n-1)-many triples, each of which has two adjacent PKG symbols in common with its neighboring triple. Presuming the existence of a least significant PKG symbol of K allows the formation of an additional triple of lesser significance. Each triple produces an associated transition bit that when set indicates, for the partial summation segment of the raw sum of bit location corresponding to the location of the triple, if the left-most two bits of the corresponding partial summation segment are, or would be with a carry-in, of opposite bit values. The bit position of the most-significant set transition bit is determined in terms of how many bit positions J that is from the most significant transition bit position. The raw sum is normalized by shifting it left by J-many bit positions and adjusting its exponent by J. If J is one too low in value then the raw sum is shifted and its exponent is adjusted by one extra count. When no transition bits are set, the raw sum is zero. A raw sum of zero does not need normalization, although the zero case needs to cause a forced a zero for the exponent. If a slightly different rule is used for determining the transition bit of the MSB, then a simplification of the rule for producing transition bits for all remaining bit positions is possible. That simplification is that any triple whose center symbol is P can produce an associated transition bit of zero.

REFERENCES:
E. Hokenek and RK Montoye; "Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit"; IBM J Res. Develop. vol. 34, No. 1; Jan. 1990; pp. 71-77.
RK Montoye, et al.; "Design of the IBM RISC System/6000 Floating-Point Execution Unit"; IBM J. Res. Develop. vol. 34 No. 1; Jan. 1990; pp. 59-70.

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