Return-to-zero current-steering DAC with clock-to-output...

Details Return-to-zero current-steering DAC with clock-to-output... Return-to-zero current-steering DAC with clock-to-output...

2008-03-25

2009-08-18

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S150000

Reexamination Certificate

active

07576675

ABSTRACT:
A return-to-zero current-steering DAC is presented. The presented return-to-zero technique can isolate the analog output nodes of the DAC from the coupling of the control signals of the DAC without sacrificing speed. The topology uses a bank of return-to-zero circuits, which employs return-to-zero and isolation transistors to implement the presented return-to-zero technique.

REFERENCES:
patent: 5331225 (1994-07-01), Matsui et al.
patent: 6545619 (2003-04-01), Segura et al.
patent: 6977602 (2005-12-01), Ostrem et al.
patent: 2007/0069810 (2007-03-01), Yang et al.
Alex R. Bugeja, A Self-Trimming 14-b 100-MS/s CMOS DAC, IEEE Journal of Solid-State Circuits, vol. 35, No. 2, Dec. 2000, pp. 1841-1852.
Jouko Vankka, A Digital Quadrature Modulator with On-Chip D/A Converter, IEEE Journal of Solid-State Circuits, vol. 38, No. 10, Oct. 2003, pp. 1635-1642.

Affiliated with

Also associated with

Rating

Return-to-zero current-steering DAC with clock-to-output... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Return-to-zero current-steering DAC with clock-to-output..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Return-to-zero current-steering DAC with clock-to-output... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4088433