Methods and apparatus for a dual-metal magnetic shield...

Active solid-state devices (e.g. – transistors – solid-state diode – With shielding

Reexamination Certificate

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C257SE23114, C257SE21665, C438S057000, C438S123000

Reexamination Certificate

active

07598596

ABSTRACT:
A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.

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patent: 6916668 (2005-07-01), Spielberger et al.
patent: 2002/0009820 (2002-01-01), Jung et al.
patent: 2002/0186011 (2002-12-01), Murata et al.
patent: 2002/0196119 (2002-12-01), Meigs et al.
patent: 2004/0223265 (2004-11-01), Ohtomo et al.
patent: 2005/0207263 (2005-09-01), Okayama et al.
patent: 2006/0222821 (2006-10-01), Masai

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