Nonvolatile semiconductor memory

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185170

Reexamination Certificate

active

07616502

ABSTRACT:
A semiconductor memory device comprising: a memory cell array having memory cell units each formed by connecting a plurality of memory cells; a first and a second select gate transistors, the first select gate transistor being connected between one end of the memory cell array and a common source line, the second select gate transistor being connected between the other end of the memory cell array and bit lines; word lines acting also as control gates of the memory cells; a first select gate voltage-generating circuit for generating a first select gate voltage; a second select gate-setting circuit for setting an instructed value of a second select gate voltage; a second select gate voltage-generating circuit for generating the second select gate voltage based on the set, instructed value; a first transfer circuit for transferring the first select gate voltage generated by the first select gate voltage-generating circuit to a second select gate; a discharging circuit for discharging the first select gate voltage transferred to the second select gate; and a discharging characteristics selection circuit for selecting discharging characteristics of the discharging circuit.

REFERENCES:
patent: 6480419 (2002-11-01), Lee
patent: 7203093 (2007-04-01), Nguyen
patent: 7206235 (2007-04-01), Lutze et al.
patent: 7259990 (2007-08-01), Maejima et al.
patent: 7369442 (2008-05-01), Lee et al.

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