Convolutional interleaver/de-interleaver

Details Convolutional interleaver/de-interleaver Convolutional interleaver/de-interleaver

1997-02-27

1999-06-15

Baker, Stephen M.

Excavating

371 22, 371 381, H03M 1322, H03M 1300

Patent

active

059128984

ABSTRACT:
An adaptable, programmable convolutional interleaving and de-interleaving system uses less space in an integrated circuit than prior art techniques, and is scalable for wide variety of values of I and M. The coder comprises a coder input receiving a stream of data in time with a clock, the stream of data being supplied in units of data such as bytes, and a coder output which supplies the interleaved or de-interleaved data. A single port RAM having an address input, a data input coupled to the coder input, and a data output coupled to the coder output is included. An address generator is coupled with the clock, and supplies a sequence of addresses to the address input in time with the clock. The sequence of addresses implements a convolutional pattern having cells with a depth equal to M units of data and having a number of rows I+1. Each row, based on an index i going from 0 to 1, includes i cells. Programmable memory is coupled to the address generator that stores a value specifying the depth M, and a value specifying the number of rows I. Logic is responsive to the stored values for M and I to generate the sequence of addresses. The convolutional pattern executed by the address generator can be either an interleaving pattern or a de-interleaving pattern as suits the needs of a particular implementation.

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