Two dimensional addressing of a matrix-vector register array

Details Two dimensional addressing of a matrix-vector register array Two dimensional addressing of a matrix-vector register array

2007-09-06

2009-02-24

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

Reexamination Certificate

active

07496731

ABSTRACT:
A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.

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