Synchronous DRAM memory with asynchronous column decode

Details Synchronous DRAM memory with asynchronous column decode Synchronous DRAM memory with asynchronous column decode

1997-09-10

1999-06-15

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

365233, G11C 800

Patent

active

059128607

ABSTRACT:
Disclosed is a synchronous DRAM memory module with control circuitry that allows the memory module to operate partially asynchronously. Specifically, a circuit is disclosed which utilizes address transition detection to begin decoding the column-address immediately after a new column-address is present on the address bus lines and without waiting for the column-address strobe signal to synchronize with the rising or falling edge of the synchronizing clock signal. Also disclosed is a manner of controlling the latching circuitry whereby each new column-address may be decoded and held within a buffer until the column-address strobe signal notifies the circuitry that the column-address is correct and is to be input into the microprocessor. Thus, each new column-address will be decoded immediately after it is present on the address lines and undesired column-addresses will be discarded, while desired column-addresses are input into the memory array bank immediately upon the presence of the column-address strobe which denotes that the column-address is final. The present invention improves the access times of read and write operations in synchronous DRAM memory by up to a complete clock cycle.

REFERENCES:
patent: 4719602 (1988-01-01), Hag et al.
patent: 4912679 (1990-03-01), Shinoda
patent: 4972374 (1990-11-01), Wang
patent: 5047984 (1991-09-01), Monden
patent: 5179535 (1993-01-01), Nakayama
patent: 5305283 (1994-04-01), Shimokura et al.
patent: 5327394 (1994-07-01), Green
patent: 5414672 (1995-05-01), Ozeki

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