Nonvolatile PMOS two transistor memory cell and array

Details Nonvolatile PMOS two transistor memory cell and array Nonvolatile PMOS two transistor memory cell and array

1997-10-09

1999-06-15

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518513, 36518518, G11C 1604

Patent

active

059128429

ABSTRACT:
A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

REFERENCES:
patent: 5554867 (1996-09-01), Ajika et al.
patent: 5615149 (1997-03-01), Kobayashi et al.
Ohnakado, T., et al., "Novel Self-limiting Program Scheme Utilizing N-channel Select Transistors in P-channel DINOR Flash Memory", IEEE pp. 181-184 (1996).
Sakamoto, O., et al., "A High Programming Throughput 0.35.mu. m P-channel DINOR Flash Memory", IEEE pp. 222-223 (1996).
Ohnakado, T., et al., "Novel Electron Injection Method Using Band-to-Band Tunneling Induced Hot Electron (BBHE) for Flash Memory with a P-channel Cell", IEEE pp. 279-282 (1995).

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