Planar NAND flash memory

Details Planar NAND flash memory Planar NAND flash memory

2007-09-21

2009-06-02

Nguyen, Tuan T (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185170, C365S185200, C365S185250, C365S189050

Reexamination Certificate

active

07542343

ABSTRACT:
Time-domain sensing scheme is introduced for reading NAND flash memory cell, wherein cell current is converted to voltage by discharging bit line, which voltage is amplified by a segment read circuit, then the voltage difference is converted to time difference by a block read circuit. In this manner, a reference signal is generated by reference cells storing low threshold data, which signal is delayed by a delay circuit for generating a locking signal. Thus the locking signal effectively rejects latching high threshold data in latch circuits because high threshold data is arrived later. Furthermore, by adopting multi-divided bit line architecture, discharging time of bit line is reduced. In addition, layout of the segment read circuit is repeatedly placed next to cell arrays in order to fabricate in the conventional planar CMOS process environment.

REFERENCES:
patent: 5465235 (1995-11-01), Miyamoto
patent: 5768215 (1998-06-01), Kwon et al.
patent: 5790458 (1998-08-01), Lee et al.
patent: 6826082 (2004-11-01), Hwang et al.
patent: 6925005 (2005-08-01), Kawamura et al.

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