Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2008-02-09

2009-12-15

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S149000, C365S194000

Reexamination Certificate

active

07633833

ABSTRACT:
The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

REFERENCES:
patent: 5619170 (1997-04-01), Nakamura
patent: 6247138 (2001-06-01), Tamura et al.
patent: 6862247 (2005-03-01), Yamazaki
patent: 2002/0024366 (2002-02-01), Ooishi et al.
patent: 7-288447 (1995-10-01), None
patent: 11-3587 (1999-01-01), None
patent: 2002-74949 (2002-03-01), None

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